1. Technical Field of the Present Invention
The present invention generally relates to integrated circuit designs and, more specifically, to verification of an integrated circuit design.
2. Description of Related Art
The manufacture of an integrated circuit has become extremely complex and expensive. As a result, simulating and testing the design of the integrated circuit prior to manufacture has become an essential requirement. Simulation and testing is performed using software, emulation systems, and the like to detect and correct design flaws.
A portion of the testing involves verification of the design. Verification of the design is often a complex and time-consuming process as a result of the millions of transistors that are typically required to implement the design. Complete design specification and verification are often not practical, particularly with complex integrated circuits and tight commercial release dates.
One approach of performing verification uses random generated test vectors. The random test vectors are applied to the design and the results compared against a correct model of the design. Random testing is time consuming and risky since there is no guarantee that all the bugs in the design will be discovered or a way to measure how well the design space was tested.
It would, therefore, be a distinct advantage to have a method, apparatus, and computer program product that would provide an indication when random testing has reached a desired level. It would be further advantageous if the random testing data was stored and tracked in a manner so as to produce a set of test data that could be used on subsequent iterations of the design.